(*DONT_TOUCH = "TRUE"*)
module pulse_generator (
    input clk,        // 系统时钟
    input rst_n,      // 同步复位信号
    input input_signal, // 控制输入
    output reg output_signal  // 模块输出
);

    // 定义计数器位宽
    localparam COUNT_MAX = 24999999; // 25,000,000 - 1
    reg [24:0] counter; // 25位计数器

    wire toggle_signal;
    assign toggle_signal = (counter == COUNT_MAX);

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            counter <= 0;
            output_signal <= 0;
        end
        else begin
            if (input_signal) begin
                if (toggle_signal) begin
                    counter <= 0;
                    output_signal <= ~output_signal; // 翻转输出信号
                end
                else begin
                    counter <= counter + 1;
                end
            end
            else begin
                output_signal <= 0; // input_signal为0时输出为0
            end
        end
    end

endmodule